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HD74CDC2509B
3.3-V Phase-lock Loop Clock Driver
ADE-205-218F (Z) 7th. Edition October 1999 Description
The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDC2509B operates at 3.3 V V CC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the HD74CDC2509B does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, HD74CDC2509B requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
Features
* * * * * Meets "PC SDRAM registered DIMM design support document, Rev. 1.2" Phase-lock loop clock distribution for synchronous DRAM applications External feedback (FBIN) pin is used to synchronize the outputs to the clock input No external RC network required Support spread spectrum clock (SSC) synthesizers
Note: Only by a change of a suffix (A to B) for standardization, there isn't any change of the product.
HD74CDC2509B
Function Table
Inputs 1G X L L H H H: L: X: High level Low level Immaterial 2G X L H L H CLK L H H H H Outputs 1Y (0:4) L L L H H 2Y (0:3) L L H L H FBOUT L H H H H
Pin Arrangement
AGND 1 VCC 2
24 CLK 23 AVCC 22 VCC 21 2Y0 20 2Y1 19 GND 18 GND 17 2Y2 16 2Y3 15 VCC 14 2G 13 FBIN
1Y0 3 1Y1 4 1Y2 5 GND 6
GND 7 1Y3 8 1Y4 9
VCC 10 1G 11 FBOUT 12
(Top view)
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HD74CDC2509B
Absolute Maximum Ratings
Item Supply voltage Input voltage
*1 *1, 2
Symbol VCC VI VO I IK I OK IO I CC or IGND PT Tstg
Ratings -0.5 to 4.6 -0.5 to 6.5 -0.5 to VCC +0.5 -50 50 50 100 0.7 -65 to +150
Unit V V V mA mA mA mA W C
Conditions
Output voltage
Input clamp current Output clamp current Continuous output current Supply current Maximum power dissipation at Ta = 55C (in still air) *3 Storage temperature Notes:
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Symbol VCC VIH VIL VI Output current I OH I OL Operating temperature Ta Min 3.0 2.0 -- 0 -- -- 0 Typ -- -- -- -- -- -- -- Max 3.6 -- 0.8 VCC -12 12 85 C mA Unit V V Conditions
Note: Unused inputs must be held high or low to prevent them from floating.
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HD74CDC2509B
Logic Diagram
1G
11 3 4 5 8 9
1Y0 1Y1 1Y2 1Y3 1Y4
2G
14 21 20 17
2Y0 2Y1 2Y2 2Y3 FBOUT
CLK FBIN AVCC
24 16
PLL
13 12
23
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HD74CDC2509B
Pin Function
Pin name CLK No. 24 Type I Description Clock input. CLK provides the clock signal to be distributed by the HD74CDC2509B clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4)are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK. Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3)are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic low state by deasserting the 1G control input. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic low state by deasserting the 2G control input. Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AV CC can be used to bypass the PLL for test purposes. When AV CC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
FBIN
13
I
1G
11
I
2G
14
I
FBOUT
12
O
1Y(0:4)
3, 4, 5, 8, 9 O
2Y(0:3)
16, 17, 20, 21
O
AVCC
23
Power
AGND VCC GND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry. Power supply
2, 10, 15, 22 Power 6, 7, 18,19
Ground Ground
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HD74CDC2509B
Electrical Characteristics
Item Input clamp voltage Output voltage Symbol Min VIK VOH -- VCC-0.2 2.1 2.4 VOL -- -- -- Input current Quiescent supply current I IN I CC I CC -- -- -- Typ *1 -- -- -- -- -- -- -- -- -- -- Max -1.2 -- -- -- 0.2 0.8 0.55 5 10 500 A A A Unit Test Conditions V V VCC = 3 V, II = -18 mA VCC = Min to Max, IOH = -100 A VCC = 3 V, IOH = -12 mA VCC = 3 V, IOH = -6 mA VCC = Min to Max, IOL = 100 A VCC = 3 V, IOL = 12 mA VCC = 3 V, IOL = 6 mA VCC = 3.6 V, VIN = VCC or GND AVCC = GND, VCC = 3.6 V, VI = VCC or GND, IO = 0 AVCC = GND, VCC = 3.3 to 3.6 V One input at V CC-0.6 V, Other inputs at V CC or GND VCC = 3.3 V, VI = VCC or GND VCC = 3.3 V, VO = VCC or GND
Input capacitance Output capacitance Note:
CIN CO
-- --
4 6
-- --
pF pF
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
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HD74CDC2509B
Switching Characteristics (CL = 30 pF, Ta = 0 to 85C)
Item Symbol VCC = 3.3 V0.3 V Min Phase error time t pe -150 Typ -- Max 150 ps 66 MHz < CLKIN 100 MHz Any Y or FBOUT F (clkin = 100 MHz) FBIN Unit
From (Input) To (Output)
Between output pins skew *1
t sk (O)
--
--
200
ps
Any Y or FBOUT Any Y or FBOUT
Cycle to cycle jitter Duty cycle Output rise / fall time t TLH t THL Analog power supply rejection (DC to 10 MHz) Notes: Vapsr *2
-100 45 5.0 5.0 100
-- -- -- -- --
100 55 1.0 1.0 --
ps % volts/ns
F (clkin = Any Y or 66 to 100 MHz) FBOUT Any Y or FBOUT Any Y or FBOUT
mVP-P
AVCC
The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 1. The t sk(O) specification is only valid for equal loading of all outputs. 2. This parameter is characterized but not tested.
Timing requirements
Item Input clock frequency Input clock duty cycle Stabilization time Note:
*1
Symbol Min f clock 50 40 --
Max 125 60 1
Unit MHz % ms
Test Conditions
After power up
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable.
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HD74CDC2509B
Test Circuit
From output under test
*1
C L = 30 pF
500
Note:
1.
CL includes probe and jig capacitance.
Waveforms - 1
3V Input 50% VCC 50% VCC 0V
Output (=FBOUT)
2V 50% VCC 0.4 V tTLH
2V 0.4 V tTHL
VOH VOL
Notes:
1. 2.
All input pulses are supplied by generators having the following characteristics: PRR 100 MHz, ZO = 50 , t r = 1.2 ns, tf = 1.2 ns. The outputs are measured one at a time with one transition per measurement.
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HD74CDC2509B
Waveforms - 2
CLKIN t phase error
FBIN
FBOUT t sk (o)
Any Y
Any Y t sk (o)
Any Y
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HD74CDC2509B
Package Dimensions
Unit : mm
7.80 8.10 Max 24 13 4.4 1 12 0.65 0.20 0.06 0.22 +0.08 -0.07 1.0 0.13 M 0.65 Max 0.17 0.05 0.15 0.04 1.10 Max 6.4 0.2 0 - 8 0.07 +0.03 -0.04 0.5 0.1 0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-24DB -- -- 0.08 g
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HD74CDC2509B
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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